物理系學術報告：III-V MOS Technology: From Planar to 3D and 4D

報告題目： III-V MOS Technology: From Planar to 3D and 4D 報告人： Peide D. Ye, Purdue University Peide D. Ye, Purdue University 報告時間： 2013年5月31日 10:00 報告地點：理科樓三樓報告廳摘要： Recently, III-V MOSFETs with high drain currents (Ids>1mA/µm) and high transconductances (gm>1mS/µm) have been achieved at sub-micron channel lengths (Lch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of deep sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V MOS technology developed very recently. We will also report some of new progress by demonstration of 20-80 nm channel length III-V gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63 mV/dec. The total drain current per pitch can be further enhanced by introducing 4D structures.Recently, III-V MOSFETs with high drain currents (Ids>1mA/µm) and high transconductances (gm>1mS/µm) have been achieved at sub-micron channel lengths (Lch), thanks to the better understanding and significant improvement in high-k/III-V interfaces. However, to realize a III-V FET at beyond 14nm technology node, one major challenge is how to effectively control the short channel effects (SCE). Due to the higher permittivity and lower bandgap of the channel materials, III-V MOSFETs are more susceptible to SCE than its Si counterpart. Therefore, the introduction of 3-dimensonal (3D) structures to the fabrication of deep sub-100nm III-V FETs is necessary. In this talk, we will review the materials and device aspects of III-V MOS technology developed very recently. We will also report some of new progress by demonstration of 20-80 nm channel length III-V gate-all-around nanowire MOSFETs with EOT=1.2nm and lowest SS=63 mV/dec. The total drain current per pitch can be further enhanced by introducing 4D structures. 個人簡介： Dr. Peide Ye is a Professor of Electrical and Computer Engineering and University Faculty Scholar at Purdue University in USA. He received the B.S. from Fudan University, Shanghai, China, in 1988 and Ph.D. from Max-Planck-Institute of Solid State Research, Stuttgart, Germany, in 1996. Before joining Purdue faculty in 2005, he worked for NTT, NHMFL/Princeton University, and Bell Labs/Agere Systems. His current research is focused on ALD high-k integration on novel channel materials include III-V, CNTs and graphene, complex oxides, topological insulators, and other 2D crystals. He authored and co-authored more than 250 peer reviewed articles and conference presentations. He is a Fellow of IEEE.